International Journal of Combined Research pISSN:2321-2241 Volume: 2; Issue: 6; June -2014

Complex number multiplication is an important arithmetic function in digital communication, radar, and optical system. Many major functions in the communication systems such as channel equalization; modulation and demodulation all deal with data streams and coefficients represented by complex numbers. Therefore efficient implementation of multiplier circuit for complex numbers is of significant importance. Consider two complex numbers, a=ar+jai and b=br+jbi and their product is P=ab=pr+jpi = (arbr-aibi) +j (arbi+aibr). The above equation shows that, the conventional implementation of this requires 4 multipliers, an adder, and a subtractor. This leads to a complex topology, since the interconnection becomes more complex, and also leads to high power dissipation. Here in this paper a new architecture has been introduced to reduce the complexity, and GDI technique has been used to reduce the power dissipation. This paper focuses two main design approaches. Initially the complex number multiplier is implemented using CMOS, and then it is compared with the GDI technique. The simulation results have shown that, the GDI consumes less power compared to CMOS. All designs were done using Cadence 90nm (GPDK 90) technology. Keywords-Complex number multiplier, Gate diffusion input (GDI), complementary metal oxide semiconductor (CMOS), Complexity, Power, D Flip flop, Multiplexer, Multiplier, Adder/ Subtractor.